1. Field of the invention
This invention relates to semiconductor structures, and, more particularly, to a semiconductor structure having conductive pillars.
2. Description of Related Art
Currently, semiconductor packages contain a wire-bonding package, a flip-chip package, etc. Compared to the wire-bonding package, the flip-chip package is better to reduce the overall volume of semiconductor devices.
A general flip-chip package acts as a semiconductor-chip surface by conductive bumps electrically bonded to conductive pads of the package substrate, and then fills in the primer between the role surface of the semiconductor chip and the package substrate, in order to cover the conductive bump. And, in order to increase the accuracy of counterpoint of the flip chip, the material of the conductive bump is very important.
Conventional semiconductor chips provide for a technology by use of copper pillars for combination, referring to FIGS. 1A to 1D.
As shown in FIG. 1A, a chip 10 having conductive pads 100 is provided. FIG. 1A shows only one conductive pad for description. The outer surface is constituted by silicon-nitride (SiN) layer 101, which exposes the conductive pads 100 through the opening of the SiN layer 101. Then, a dielectric layer 12 is formed on the silicon-nitride layer 101 and on the wall surface of the opening. A titanium (Ti) layer 11 is formed on all the surfaces of the dielectric layer 12 and on the conductive pads 100. A copper (Cu) layer 13 is formed on all the surfaces of the titanium layer 11.
As shown in FIG. 1B, a resist layer 14 is formed on the copper layer 13, and an opening area 140 is formed on the resist layer 14, in order to expose a portion of the copper layer 13. Copper pillars 15 are formed on the copper layer 13 within the opening area 140. A solder material 16 is formed on a top surface of the copper pillars 15.
As shown in FIG. 1C, the resist layer 14 is removed, in order to expose the copper layer 13.
As shown in FIG. 1D, the copper pillars 15 function as stopper portions in order to remove the exposed copper layer 13 and the underneath titanium layer 11 by etching. In the follow-up fabrication process, the solder bump can be formed on the copper pillars 15 and solder material 16 in order for butt joint to the package substrate (not shown). Then a reflow process is performed in order to form the conductive bump which is for immobilization and for electrical connection between the chip 10 and the package substrate.
When the reflow process is performed, the copper pillars 15 would not deform so they can avoid melt and collapse. The copper pillars 15 can prevent traditional chips 10 from deviating. Thus, the copper pillars 15 in the conductive bump can increase the accuracy of counterpoint of the flip chip.
However in the method of fabricating the semiconductor structure, the incident of inward etching would occur because there is isotropy if using etching liquid to etch. So when the exposed copper layer 13 and the underneath titanium layer 11 are removed by etching, the titanium layer 11 would lead to the problem of overlarge undercut (as shown in the undercut area K of FIG. 1D). It results in non-enough support of the copper pillars 15 and results in decreased product reliability because of the bad conductive bump.
Hence, the problem of overlarge undercut which decreases product reliability in prior art is indeed a target to be solved.